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2010-2012 Microchip Technology Inc.
DS39977F-page 141
PIC18F66K80 FAMILY
8.3
Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADRH:EEADR register pair, clear the
EEPGD control bit (EECON1<7>) and then set control
bit, RD (EECON1<0>). The data is available after one
instruction cycle, in the EEDATA register. It can be read
after one NOP instruction. EEDATA will hold this value
until another read operation or until it is written to by the
user (during a write operation).
The basic process is shown in Example 8-1.
8.4
Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADRH:EEADR register pair
and the data written to the EEDATA register. The
sequence in Example 8-2 must be followed to initiate
the write cycle.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, EECON1,
EEADRH:EEADR and EEDATA cannot be modified.
The WR bit will be inhibited from being set unless the
WREN bit is set. The WREN bit must be set on a
previous instruction. Both WR and WREN cannot be
set with the same instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag bit
(EEIF) is set. The user may either enable this interrupt
or poll this bit; EEIF must be cleared by software.
8.5
Write Verify
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
Note:
Self-write
execution
to
Flash
and
EEPROM memory cannot be done while
running in LP Oscillator (low-power)
mode. Executing a self-write will put the
device into High-Power mode.
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